Dual damascene interconnects may enable reliable low cost production of integrated microelectronic circuits using sub 0.18 micron process technology. Process flows utilizing sacrificial light absorbing materials (“SLAM”) may be employed to facilitate very small feature size dual damascene interconnects. With such techniques, a first etched region (e.g., a via or trench) may be filled with a sacrificial light absorbing material (“SLAM”), after such region has been formed within a dielectric layer. The SLAM preferably comprises a material having dry etch properties similar to those of the dielectric layer and anti-reflective (or light absorbing) properties that prevent lithographic-related defects during subsequent photoresist processing. After the first etched region is filled with the SLAM, a second etched region (e.g., a trench if the via is already formed or a via if the trench is already formed) may be formed within the dielectric layer. Some of the SLAM is removed as that second etched region is formed, as both the SLAM and the dielectric are etched. Remaining portions of the SLAM subsequently may be removed with a wet etch step or other conventional selective removal technique which does not significantly etch or alter the dielectric material.
SLAM process integrations utilizing appropriately matched materials may reduce, or eliminate, substrate reflection and the need for high etch selectivity, ensuring that such effects will not adversely affect dual damascene via and trench formation. Current SLAM materials utilized for substantially defect-free patterning are formulated for compatibility with conventional silicon oxide based dielectric materials in both etch rate and removability. To facilitate substantially defect-free patterning of polymer-based dielectric materials in process integration scenarios such as dual damascene, SLAM materials with etch and clean characteristics compatible with such polymer-based dielectric materials (i.e., “polymer SLAM” materials) are needed.
Absent preferable polymer SLAM materials, dual damascene integrations for polymer-based interlayer dielectric (“ILD”) materials have been developed wherein dual hardmask process flows are employed. Such process flows are increasingly complex, providing potential sources of defects, and can be prohibitively expensive to implement in a manufacturing environment. Other dual damascene integrations for polymer-based ILD materials have utilized antireflective coating materials, such as “bottom organic antireflective coating” layers or “BOARC” layers. The implementation of BOARC layers in polymer dual damascene patterning, however, has been associated with problems due to inexact matching of etch rates between the BOARC materials and the polymer ILD materials, leading to defects known as “shell defects” and “microtrenching” or “cratering”. Referring to FIGS. 1A and 1B, depictions of shell and crater defects are depicted. Additionally, the inability to effectively remove BOARC materials in the presence of polymer ILD materials in some instances can lead to additional process integration difficulties.
Accordingly, there is a need for materials and integration schemes to allow efficient dual damascene patterning with polymeric dielectric materials by substantially matching etch rates of subject polymeric dielectric materials with polymeric SLAM materials to facilitate removal of the SLAM after pertinent process treatments without damaging adjacent polymeric dielectric structures.